The basic structure of a prior art word synchronization circuit is shown in FIG. 13. In the figure, a syndrome calculating circuit 100 calculates a so-called syndrome of input data on a word by word basis, based on word synchronization signals output from a word counter 102. An error pulse E is output whenever the calculated syndrome is not zero. A testing circuit 103 receives the error pulse E as input. When the error pulses E are output continuously for the N stages of a predetermined sync-in testing circuits, the circuit 103 determines the situation as one where the word synchronization has not yet been established. The phase 0 of the word counter 102 is then shifted by one bit. The testing circuit 103 determines that, when the syndrome calculated by the syndrome calculating circuit 100 stays zero for a sequence of M times, a word synchronization has been established.
The above operation can be expressed numerically as follows. More particularly, the received signals can be expressed as a polynomial as follows: EQU R.sub.0 (X)=a.sub.0 X.sup.n-1 +a.sub.1 X.sup.n-2 +. . . +a.sub.n-2 X+a.sub.n-1 . . . ( 1)
wherein the received signals are represented by EQU . . . a.sub.-2, a.sub.-1, a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-n, a.sub.n . . .
and signals of a correct block by EQU a.sub.0, a.sub.1, . . . a.sub.n-1.
where the symbol + represents the addition which occurs in modules 102 herein. A polynomial representation R.sub.k (X), of a received signal which is slipped, or out-of-phase by k bits then becomes as follows: EQU R.sub.k (X)=a.sub.k X.sup.n-1 +a.sub.k+1 X.sup.n-2 +a.sub.n+k-1 X+a.sub.n+k-1 . . . ( 2)
If it is assumed that the root of a generator polynomial G(X)=0 is a, a, the value of the syndrome can be obtained by substituting X=.alpha. in the receiver polynomial. Therefore, the syndrome at the correct initial phase becomes as follows: ##EQU1## The syndrome at the initial phase, slipped by one bit, can be obtained from the expression below. ##EQU2## When a.sub.n =a.sub.0, the syndrome becomes zero. Similarly, syndromes at phases which have slipped by one or two bits can be expressed as below. ##EQU3##
Therefore, when the initial phase has slipped in either direction by one or two bits, the probabilities of the syndrome being zero are 1/2 and 1/4 respectively. The word synchronization is established when a word with a syndrome of zero continues for the sequence of M times, as sync-in testing circuits are generally provided in a word synchronization circuit. Accordingly, synchronization slips at the probabilities of (1/2).sup.M, (1/4).sup.M, . . .
When synchronization slip occurs, the error pulses are counted by a sync-out testing circuit according to the prior art circuit structure, and the error pulses are generated for the sequence of N times. The situation leads to a determination that the synchronization has been lost, and the word synchronization is reset once again.
However, the prior art method is detrimental in that when N is a large number, that is the sequence of N times is very long, synchronization slip can be detected only after it is repeated N times in the process of establishing synchronization. This effectively increases the time needed for synchronization slip detection. It further prolongs the time needed for recovery of normal operation. If the number of times N is made excessively small, on the other hand, even if synchronization has been established, bit errors may be erroneously detected as synchronization slip, and cause re-initiation of the process of establishing synchronization, to disturbing the actually stable synchronization.
The present invention aims to solve the above-mentioned problems encountered in the prior art, and to provide a word synchronization system which can detect the conditions of synchronization slip, if occurring, as well and as quickly and merely is less likely to detect a synchronization slip if a small number of bit errors are caused in transmission signals.
A first aspect of this invention defines a word synchronization system with a syndrome calculating circuit which receives encoded signals including forward error correction codes and calculates a syndrome from an initial phase. A controlling means changes the initial phase of the circuit when the syndrome calculated by said circuit is not zero and again calculates the syndrome. When the syndrome becomes zero, the system calculates the syndrome from the same initial phase by a sync-in testing circuit. The operation is repeated until the time the syndrome becomes zero for the sequence of M times to establish synchronization.
A synchronization slip detecting circuit is provided for outputting signals for slipping and judges that word synchronization has been lost when it detects a particular syndrome after synchronization has been established for more than K.sub.0 times in the sequence of K items (K.sub.0 .ltoreq.K.ltoreq.M).
The particular syndrome as used herein is a syndrome which is not zero and in which an error pulse appears at the first bit of a word.
The second aspect of this invention defines a word synchronization system which synchronizes words commonly for the signals from m plural systems having the same initial phases comprising one each circuit for m systems which receives encoded signals having the same initial phases and including forward error correction codes to calculate the syndrome from one initial phase. The initial phase is changed when the syndrome calculated by the circuit is not zero until the time the syndrome is continuously zero for the sequence of M times, and a means which issues word synchronization pulses when the syndrome is continuously zero for the sequence of M times and which is provided one each for m systems. A synchronization slip detecting circuit outputs signals indicative of a slip in the word synchronization when the syndrome of all the systems or all the m systems become a particular syndrome.
The third aspect of this invention lies in a system for word synchronization which can synchronize signals respectively for the plural m systems having initial phases identical to each other. A circuit receives encoded signals including error correction codes of plural systems having identical initial phases to each other, and the initial phase is changed when the calculated syndrome is not zero until the syndrome becomes zero for the sequence of M times. Word synchronization pulses are issued when the syndrome becomes zero for the sequence of M times, the above circuits being provided one for each of the systems respectively. The invention system has a synchronization slip detecting circuit which detects whether or not the phases of all the word synchronization pulses are identical to each other in all of the m systems. If not identical signals indicative of slipping of word synchronization are produced.
The fourth aspect of this invention is a system which employs Gray codes and which comprises a circuit for receiving multi-value signals which have been separately encoded into codes for each system with error correction codes and further encoded into Gray codes and which calculates the syndrome from one initial phase. A controlling means changes the initial phase of the circuit if the calculated syndrome is not zero, calculates it once more, and repeats the operation until the syndrome becomes zero for the sequence of M times. A synchronization slip detecting circuit which includes a gate circuit to detect synchronized generation of error pulse signals for indicating the positions of code errors in respective systems, and a testing counter which outputs signals for slipping in the word synchronization when the output from the above circuit is detected for more than K.sub.0 times in the sequence of K (K.sub.0 .ltoreq.K).
A method of operating such a device is also contemplated.
Using the signal indicative slipping in word synchronization mentioned above, it becomes possible to change the initial phase or to reset the word synchronization, or both.
According to this invention, secured performance is guaranteed even if the number of stages, M, is set as a large number, and since a synchronization slip detecting circuit is provided separately, the judgement of the synchronization slip can be made quickly without the necessity of waiting for the M time repetition to immediately proceed to the phase reset or synchronization step. As it is least likely for the synchronization slip detecting circuit to judge bit errors in transmission of signals as a synchronization slip, stable synchronization can be maintained.